The inventive concepts described herein relate to a memory device.
FIG. 1 is a circuit diagram illustrating a conventional static random access memory bit-cell. As illustrated in FIG. 1, a conventional SRAM bit-cell includes eight transistors including a cross-coupled inverter pair (IN1, IN2) and stores logic 0 and logic 1 at two data storage nodes, respectively. During a write operation, pass gate transistors PG1 and PG2 connect bit lines BL and BLB with the data storage nodes, respectively. A signal is shared by bit-cells arranged along the row direction and is transmitted to the bit-cells through a word line WL and makes it possible to turn on or off the pass gate transistors. A signal is shared by bit-cells arranged along the column direction and is transmitted to the bit-cells through the bit lines BL and BLB.
During a read operation, a ground voltage (i.e., 0 V) is applied to the word line WL, and a supply voltage is applied to the bit lines BL and BLB and a word line for read operation RWL. According to this bias condition, a bit line for read operation RBL is changed from the supply voltage to a floating state, and information stored at a bit-cell is read by detecting a current which flows through read buffer transistors N1 and N2. A current flowing through the read buffer transistors N1 and N2 during the read operation is prevented from flowing into a data storage node, and data stored at a bit-cell is prevented from flipping due to a current flowing during the read operation. Accordingly, read stability is improved. However, in the case of a conventional SRAM, data flip occurs in a row half-selected bit-cell during a write operation due to a half-select issue.
FIG. 2 is a circuit diagram for describing a problem which occurs in a row half-selected bit-cell during a write operation of a conventional SRAM. In FIG. 2, during a write operation, a first bit-cell placed at the left is a bit-cell in which a write operation is performed, and a second bit-cell placed at the right is a bit-cell in which a write operation is not performed. The case mostly occurs in a SRAM having a bit-interleaving structure. The bit-interleaving structure refers to a structure arranged such that bit-cells belonging to different words are arranged to be adjacent to each other. That is, in the bit-interleaving structure, bit-cells belonging to the same words are not arranged to be adjacent to each other. The bit-interleaving structure makes it possible to prevent data of some bit-cells in the same word from being simultaneously lost due to a soft error. Moreover, even though the soft error occurs, the bit-interleaving structure makes it possible to minimize the loss of data in the same word. Accordingly, it is possible to recover data easily.
Referring to FIG. 2, the first bit-cell and the second bit-cell belong to different words from each other. When a write operation about a word to which the first bit-cell placed at the left belongs is performed, a supply voltage VDD is also applied to the word line WL of the second bit-cell placed at the right. Accordingly, current flows into a data storage node, in which logic 0 is stored, through the pass gate transistor PG1 and a pull-down transistor PD1 of a cross-coupled inverter at the second bit-cell placed at the right. Accordingly, a read disturbance such as the data flip occurs at the second bit-cell (i.e., a row half-selected bit-cell).
To solve the read disturbance occurring at a row half-selected bit-cell during a write operation, after data in all of row half-selected bit-cells is read before the write operation is performed, an operation to write information thus read at a row half-selected bit-cell is again performed. This is referred to as “write-back operation”. However, because a read operation and a write operation are performed with respect to all row half-selected bit-cells in a write-back operation whenever a write operation is performed, power consumption is very much.
FIG. 3 is a circuit diagram illustrating another example of a conventional SRAM structure. In a SRAM of FIG. 3, the pass gate transistors PGL1 and PGR1 placed at the right are turned off during a write operation of the first bit-cell placed at the left, thereby preventing a read disturbance at a row half-selected bit-cell without a write-back operation. That is, in the SRAM of FIG. 3, a supply voltage is applied to both a word line WLR in the row direction and a word line WLC in the column direction, and thus a write operation is performed only at one selected bit-cell. However, the SRAM of the above-described structure necessitates ten transistors per bit-cell, thereby causing an increase in an area per bit-cell and making it difficult to miniaturize a memory.